0x0005 Message not used %s\n
0x0006 %s\n
0x0007 -- %s %s --\n
0x0008 -- %s version %s -- built number %d --\n
0x0009 internal error, unknown message number\n
0x000a %s
0x000b unable to allocate memory\n
0x0010 Information
0x0011 Warning
0x0012 Error
0x0013 Fatal error
0x0014 Panic error
0x0015 NORMAL
0x0016 WARNING
0x0017 ERROR
0x0018 FATAL
0x0019 PANIC
0x001A ECHO
0x0020 unable to allocate buffers\n
0x0100 unable to allocate dynamic buffer stack\n
0x0101 invalid history depth\n
0x0102 unable to allocate dynamic history stack\n
0x0103 h%d %s
0x0104 history number too large or null, ignored\n
0x0105 file %s too large, setup an alternate editor\n
0x0106 error or user cancel on creating new version, process canceled\n
0x0107 error or user cancel on creating new component, process canceled\n
0x0108 error on creating instance, process canceled, Backup restored\n
0x0109 error on editing resources, process canceled, Backup restored\n
0x010a error on inserting DFT, process canceled, Backup restored\n
0x010b file path %s too large, limited to %d characters\n
0x010c unable to allocate stdin input file descriptor\n
0x010d unable to allocate stdin input buffer\n
0x010e unable to allocate input file descriptor\n
0x010f unable to allocate input buffer\n
0x0110 unable to open file %s\n
0x0111 unexpected end of file on input file %s, ignored\n
0x0112 parameter index too large, ignored\n
0x0113 parameter too long, truncated to maximum size %d\n
0x0114 parameter $%d not defined, replaced by null string\n
0x0115 %s completion\n
0x0116 prompt too long, truncated to maximum size %d\n
0x0117 option unknown\n
0x0118 --> error in file %s at line %d near token %s : %s\n
0x0119 unable to build new data base, file %s already exists\n
0x011a error on rebuilding source, process canceled, Backup restored\n
0x011b error on creating tap & scan files, process canceled, Backup restored\n
0x011c This Database is locked.\n\nIt is currently used by a other user or\ndidn't correctly closed after a previous session.\n\n- "Cancel" to cancel the current operation.\n- "OK" to reset the lock and continue.\n    (this can cause dammage if it is already in use)
0x011d unable to open the lock file %s\n
0x011e unable to unlock file %s, contact your administrator\n
0x011f loading error, library %s not defined\n
0x0120 unable to delete file %s\n
0x0121 Database %s refers to library %s whose path is invalid (%s). Please select a valid path for %s.\n
0x0122 %d invalid component library path found. Please fix path in workspace.\n
0x0123 invalid path (%d chars max).\n
0x0124 A library already exists with this path.\n
0x0125 This logical name is already used.\n
0x0126 Analysis failed. Please consult Analysis Report for further informations
0x0127 As JTAG scan chain changed, cluster test files must be imported and TUC initialization files must be re-created. \n
0x0128 Importing automatically connector mapping of board %s into system %s.\n
0x0129 Removing automatically connector mapping of board %s from system %s.\n
0x012A NetList Mapping file could not be loaded (%s). Please check NetList Analysis report for more information.\n
0x012B Check coherency with Tests Under Condition (TUC)\n
0x012C The directory %s was not completely deleted.\n
0x012D unable to open file %s\n Please check the cluster interface\n
0x012E Analysis failed. Please consult console for further informations
0x012F Unable to open file %s for writting. Please check file properties.
0x0130 Incoherency in the file %s for mapping %s : connector %s not found in netlist.\n
0x0131 Incoherency in the file %s for mapping %s : connectors %s and %s not found in netlist.\n
0x0132 The pin %s/%s does not exist!
0x0133 The pin mapping %s/%s from mapping %s will be removed.
0x0134 Importing automatically tuc(s) of board %s into system %s.\n
0x0135 Removing automatically tuc(s) of board %s from system %s.\n
0x0136 File importation aborted! (%s)
0x0200 log file......... : %s\n
0x0201 logging.......... : %s\n
0x0202 log stamping time : %d minute(s)\n
0x0203 log index maximum : %d\n
0x0204 warning number... : %d\n
0x0205 error   number... : %d\n
0x0206 fatal   number... : %d\n
0x0207 panic   number... : %d\n
0x0208 interpreter echo. : %s\n
0x0209 temento mode..... : %s\n
0x020a message file..... : %s\n
0x020b prompt........... : %s\n
0x020c parameter $%d.... : %s\n
0x020d log stamping..... : %s\n
0x020f Missing license file
0x0210 Security library initialization error\n
0x0211 license manager Error : %s (%s)\n
0x0212 the license (%s) will expire tonight!\n
0x0213 the license (%s) will expire in %d days!\n
0x0214 license file not found\n
0x0215 the feature '%s' is not enabled by your current license\n
0x0216 product is %s, version is %s\n
0x0217 unable to run DiaLite Production without hardware socket %s\n
0x0218 unable to run DiaLite Production without hardware slot %s\n
0x0219 unable to run DiaLite Production without Unit to test\n
0x021A Unable to get component definition of %s for DiaLite Production
0x021B unable to run DiaLite Production without TestPlan\n
0x021C unable to run DiaLite Production : missing socket, slot, or test plan\n
0x021D invalid password\n
0x021E please fill in the operator ID\n
0x021F please fill in the UUT serial number\n
0x0220 please fill in the product name\n
0x0221 the feature '%s' is limited to %d elements by your current license\n
0x0222 Test plan '%s' already created\n
0x0223 Parm1 '%s', Parm2 '%d', Parm3 '%c', Parm4 '%f', Parm5 '%s', \n
0x0224 "Interconnect test (JTAG)..."
0x0225 "Verifying JTAG chain..."
0x0226 "Interconnect test (Clusters)..."
0x0227 "Test file '%s' not found"
0x0228 "Interconnect errors found : %s"
0x0229 "Base path is not valid. Default path will be used"
0X022A no product list found in DiaTem.ini file\n
0X022B product field missing in production settings\n
0X022C socket field missing for product %s\n
0X022D slot field missing for product %s\n
0X022E test plan field missing for product %s\n
0X022F language field missing for product %s\n
0x0230 License not available\n
0x0231 Invalid initialization parameter value\n
0x0232 Could not convert SVF file into TTS file
0x0233 Socket properties directory not specified.
0x0234 Error in test plan execution
0x0235 unable to run DiaLite Production without Product %s\n
0x0236 Component not found. Please check the settings\n
0x0237 please fill in all the field needed\n
0x0238 Socket does not support running TTS file\n
0x0240 Some prefix (R, PU, PD, ...) have their transparency tables empty, while they should usually be set. 
0x0241 Instance name %s already used.\n
0x0242 Unable to update parameters: missing socket, slot, or test plan\n
0x0300 unable to open message file %s\n
0x0301 read error on message file %s\n
0x0302 unexpected end of file on message file %s\n
0x0303 unable to allocate dynamic message stack\n
0x0304 instruction %s is private, replaced by %s\n
0x0305 error on file(s) backup, operation canceled\n
0x0306 reduced netlist without net, check instance type prefixes\n
0x0307 invalid value, modification canceled\n
0x0308 cannot update a cluster\n
0x0309 cannot create cluster on component not hardware\n
0x030a cannot reduce a netlist without net(s)\n
0x030b error or user cancel on creating cluster, process canceled\n
0x030c error in processing the dictionary, must exit the debugger\n
0x030d error in processing the dictionary, %s [%d] out of bound\n
0x030e Command was canceled.\n
0x030f Cluster '%s' has not been tested because it has not been defined\n
0x0310 Error in the definition of cluster %s\n
0x0311 if %s is a JTAG chip, import its BSDL,\nelse define the surrounding cluster\n
0x0312 Netlist operations have not been completed
0x0313 Please describe the block first,\nby importing a source file, importing a BSDL,\nor describing it\n
0x0314 Please merge the netlists first\n
0x0315 cluster %s : unknown kind %d
0x0316 cluster %s : missing signal declaration for %s.\n
0x0317 The flash (%s, %s) access protocol has not been saved, please check the "flash access protocol" step manualy.
0x0318 The cluster interface for cluster %s has not been saved%s. Please check the "cluster interface instance" step manualy.
0x0319 The cluster interface for cluster %s has been correctly saved.
0x0320 The component description cannot be mapped to the TemTag socket with the MultiPort selection\nPlease check the TemTag V1 socket settings\n
0x0321 The flash (%s, %s) access protocol has been correctly saved.
0x0400 closing log file %s\n
0x0401 log file %s open\n
0x0402 unable to open log file %s, logging disabled\n
0x0403 value %d less than minimum log file index %d\n
0x0404 value %d greater than maximum log file index %d\n
0x0405 log stamping disabled\n
0x0406 %s loading error, operation canceled\n
0x0407 component database logical name missing or wrong\n
0x0408 dft library logical name missing or wrong\n
0x040e the components do not have the same type\n
0x040f the components do not have the same parent component\n
0x0500 unable to allocate dynamic os call stack\n
0x0501 file extension too long %s\n
0x0502 process file name too long %s\n
0x0503 process file table full\n
0x0504 file with extension %s opened by process %s\n
0x0505 cannot find extension file %s\n
0x0506 unable to execute the shell command %s\n
0x0507 unable to find extension %s in process table\n
0x0508 unable to allocate dynamic process stack\n
0x0509 execution canceled by user\n
0x0600 button number %d larger than maximum %d\n
0x0601 button number %d already defined\n
0x0602 unable to find file.  %s (%s)\n
0x0603 unable to allocate dynamic button stack\n
0x0604 button %d (%s) associated to command %s\n
0x0605 button %d is not defined\n
0x0606 Unable to load Kernel object "%s" due to child "%s" : %s\n
0x0607 Unable to validate Kernel object "%s" due to child "%s"\n
0x0608 Unable to validate Cluster instance "%s", missing model "%s"\n
0x0700 unable to write temporary file %s\n
0x0701 unable to open temporary file %s\n
0x0702 unable to execute temporary file %s\n
0x0703 command not implemented in this version\n
0x0704 unable to find directory %s\n
0x0705 unable to create file %s\n
0x0706 unable to copy file %s\n
0x0707 %s : section %s, line %d, processing stopped\n
0x0708 %s name not defined\n
0x0709 cluster type not defined\n
0x0800 cannot work with root\n
0x0801 component to copy must be selected by version\n
0x0802 component version must be added to a rooted component\n
0x0803 maximum version number is 99, unable to add component version\n
0x0804 component to copy must be a rooted component\n
0x0805 paste target must be a component version\n
0x0806 must copy a component before paste\n
0x0807 component to cut must be selected by version\n
0x0808 component to cut cannot be a rooted component\n
0x0809 unable to allocate component descriptor\n
0x080a delete only version\n
0x080b delete only a version of a rooted component\n
0x080c you may have to remove manually the instances in the source code\n
0x080d cannot paste on itself\n
0x080e cannot delete a component utilized\n
0x080f unable to open component database file\n
0x0900 %s: duplicate component name\n
0x0901 %s: duplicate component version\n
0x0902 %s: invalid version number\n
0x0903 load tap only on rooted asic or rooted asic version\n
0x0904 cannot find tap controller file\n
0x0905 cannot allocate tap controller descriptor\n
0x0906 tap controller not defined\n
0x0907 unable to allocate dictionary entry\n
0x0908 invalid character -> %c <- in name %s\n
0x0909 unable to load scan data register file\n
0x090a linkage error\n
0x090b error in compiling file %s\n
0x090c generic parameter(s) may not be defined\n
0x090d socket does not need to be composed\n
0x090e unable to connect the socket hardware\n
0x090f command %s not implemented in this socket\n
0x0910 invalid first character ->%c<- in name %s (a letter is expected)\n
0x0911 invalid last character ->%c<- in name %s\n
0x0912 New TAP could not be inserted as maximum number of licenced TAP (%u) has been reached.\n
0x0913 command %s not implemented in this socket. Please check test file : %s\n
0x0a00 unable to allocate data register buffer\n
0x0a01 unable to create socket interface file %s\n
0x0a02 unable to establish the connection with the socket\n
0x0a03 tool self disconnection\n
0x0a04 unable to load the socket executable file %s\n
0x0a05 Socket not available\n
0x0a06 unable to load the language executable file %s\n
0x0a07 %s : file %s, line %d, processing stopped\n
0x0a08 %s: duplicate resource name\n
0x0a09 invalid character ->%c<- in instance name %s\n
0x0a0a %s: duplicate instance name\n
0x0a0b generate : missing range(s)\n
0x0a0c the socket cannot handle the language(s) of the unit under test\n
0x0a0d unable to locate the socket process\n
0x0a0e socket cannot handle more than 1 pinout connection\n
0x0a0f socket cannot handle mixture of pinout and tap connection\n
0x0a10 invalid resource definition: remaining empty fields\n
0x0a11 more than one 'TemTagV1-XXXX.dll' found
0x0b00 unable to establish the socket interface\n
0x0b01 test already analyzed. Opening archive %s\n
0x0b02 no archive, unable to run test %s analysis\n
0x0b03 unable to produce analysis, analyze test %s before\n
0x0b04 unable to produce regression, analyze test %s before\n
0x0b05 unable to produce regression, need at least one test %s analysis archive\n
0x0b06 test %s empty curve data file\n
0x0b07 unable to find test %s curve data file\n
0x0b08 cannot analyze concurrently more than %i tests\n
0x0b09 cannot apply correlation analysis on more than %i signals\n
0x0b0a unable to apply correlation analysis on IN signal type\n
0x0b0b unable to produce stuck at fault analysis, analyze test %s before\n
0x0b0c unable to produce correlation fault analysis, need at least one data input\n
0x0b0d unconsistent names between .tts and .tas files\n
0x0b10 uncompatible language between component. Cannot paste\n
0x0b11 Can't have two instances of the same cluster in the same place. Cannot paste\n
0x0bc1 internal BitPag error! please complete bug report with bug ID #%s\n
0x0bc2 netlist format not recognized yet\n
0x0bc3 insufficient memory\n
0x0bc4 the %s component is not referenced in the netlist, please check and restart\n
0x0bc5 must select a Netlist File\n
0x0bc6 must select a Pattern File\n
0x0bc7 component instance <%s> not referenced in the Database\n
0x0bc8 logical pin <%s> do not exist for component instance <%s>\n
0x0bc9 BitPag process completed without error detected\n
0x0bca BitPag process completed with %i error(s), see report\n
0x0bcb Netlist was reduced. Must reload the Debugger\n
0x0bcc JTAG-Interconnect script '%s' failed (%s)\n
0x0bcd Unable to generate new prefix. <%s> is duplicated\n
0x0bce Aborted testing this net or group of nets\n
0x0bcf JTAG-Interconnect script '%s' <STRONG style="color: red">failed</STRONG> (%s)\n
0x0bd0 Result for test %s
0x0bd1 Test failed
0x0bd2 Could not run test
0x0bd3 Test OK
0x0bd4 Canceled by user
0x0bd5 Test not executed
0x0bd6 Test %s : %s
0x0bd7 Invalid net list. Missing prefix for %s. check netlist before running BitPag.
0x0be0 Error on SDR Statement : differences between actual and expected value:\nActual: %s Exp: %s Mask: %s\n
0x0be1 Error on SIR Statement : differences between actual and expected value:\nActual: %s Exp: %s Mask: %s\n
0x0be2 SVF file %s started\n
0x0be3 SVF file %s correctly processed\n
0x0be4  %d error(s), %d warning(s) in SVF file %s
0x0c00 unable to calculate TBC delay, forced to %d\n
0x0c01 Error found : see report\n
0x0c02 Scan path(s) successfully verified\n
0x0c03 Only %d's have been read, please check: socket properties, connection to the UUT, UUT power supply, JTAG clock period.\n
0x0c04 Check Scan failed! Further flash actions may fail\n
0x0d01 must select a file!\n
# 0x0d02 cannot start %s\n
# 0x0d02 FORK system call failed, possibly too many processes running?\n
0x0d03 must set Connector settings in the Socket Composer window!\n
0x0d04 cannot execute %s \n
0x0d05 segmentation fault! please complete bug Report\n
# 0x0d06 bus Error! please complete bug report\n
# 0x0d06 illegal instruction! please complete bug report\n
0x0d07 cannot load DLL file: <%s>, incorrect symbol table?\n
0x0d08 no editor are defined. Select one in the Diatem settings dialog box\n
0x0d09 Requested %s can bot be set! Please update value\n
0x0df0 Type of component used during conversion process is not valid
0x0e00 first time you run Diatem, please configure workspace\n
0x0f00 internal scan %s insertion failed\n
0x0f01 unable to import BSDL file, no file selected\n
0x0f02 unable to import BSDL file, errors found\n
0x0f03 unable to open tap file %s\n
0x0f05 unable to create %s scan file\n
0x0f06 partial instance range specification\n
0x0f07 unable to allocate resource buffer\n
0x0f08 unable to find the template file %s\n
0x0f09 error has been found: DFT insertion operation cancelled\n
0x0f0a unsupported language for this socket\n
0x0f0b timeout reached on receive response\n
0x0f0c DFT insertion has created a new component version : %s-%s
0x0f10 get WinSock DLL information failed\n
0x0f11 incompatible WinSock DLL version\n
0x0f12 socket not initialized\n
0x0f13 socket failed\n
0x0f14 setsockopt failed\n
0x0f15 bind failed\n
0x0f16 listen failed\n
0x0f17 accept failed\n
0x0f18 connect failed\n
0x0f19 unknown server address\n
0x0f1A connection closed by the remote\n
0x0f1B receive failed\n
0x0f1C send failed\n
0x0f1D wrong data size\n
0x0f1E remote failure\n
0x0f1F wrong input data\n
0x0f20 %s file %s import started\n
0x0f21 %s file %s import correctly processed\n
0x0f22 \n%d error(s), %d warning(s) in %s file %s, process canceled\n
0x0f23 \n%d warning(s) in %s file %s\n
0x0f24 no Default Pin Mapping defined, problems will occur in the debugger\n
0x0f25 Please select the instruction of instance %s of comp %s , as needed.\n
0x0f26 %s file correctly imported\n
0x0f27 Please select the Cluster/Enable mode.\n
0x0f28 %s file %s import, process canceled\n
0x0f29 %sProcess canceled\n
0x0f2a Bypass statement: %s\n
0x0f2b EDIF version: %s\n
0x0f2c wrong Edif level\n
0x0f2d wrong port direction\n
0x0f2e wrong view type\n
0x0f2f wrong cell type\n
0x0f30 the %s file %s is currently loaded\n
0x0f31 unknown instance %s\n
0x0f32 inconsistency instance %s\n
0x0f33 unknown view of instance %s\n
0x0f34 unable to find a view of the instance %s\n
0x0f35 unknown port %s\n
0x0f36 inconsistency port %s\n
0x0f37 unknown cell %s\n
0x0f38 inconsistency net definition\
0x0f39 inconsistency instance definition\n
0x0f3a current Keyword Level not supported\n
0x0f3b current Edif Version not supported\n
0x0f3c current Edif Level not supported\n
0x0f3d no pin number defined for %s (%s)\n
0x0f3e no instance type defined for %s\n
0x0f3f unable to build the netlist, no design/library defined\n
0x0f40 IEEE1149 stable state not supported, IDLE assumed\n
0x0f41 scan pattern redefinition\n
0x0f42 incoherency pattern definition\n
0x0f43 incoherency Min and Max time value\n
0x0f44 unexpected TRST statement\n
0x0f45 the PIO already exists\n
0x0f46 empty PIOMAP statement\n
0x0f47 multiple PIO definition for the same column\n
0x0f48 no continuous PIO column number\n
0x0f49 unexpected PIOMAP statement\n
0x0f4a unknown library %s\n
0x0f4b unknown cell %s refrenced by library %s\n
0x0f4c incoherency pattern definition. Empty pattern assumed.\n
0x0f4d incoherency pattern definition. Pattern will be truncated.\n
0x0f4e File %s import started\n
0x0f4f File %s import correctly processed\n
0x0f50 wrong size for IR pattern\n
0x0f51 wrong size for DR pattern\n
0x0f52 unknown IR code\n
0x0f53 MSB bits set to zero to match register size\n
0x0f54 unable to build the netlist, cell %s not defined\n
0x0f55 unable to build the netlist, no netlist view defined\n
0x0f56 unable to complete the netlist, no instance has been found\n
0x0f57 unable to complete the netlist, no net has been found\n
0x0f58 unable to complete the netlist, no instance and no net has been found\n
0x0f59 Write protocol not defined.\n
0x0f5a Read protocol not defined.\n
0x0f60 CAP definition file already loaded\n
0x0f61 Error occurs during saving process of cap file: %s
0x0f62 Erase sector protocol not defined.\n
0x0f63 CAP definition file, wrong keyword\n %s
0x0f64 CAP definition file, wrong signal record\n %s
0x0f65 CAP definition file, wrong operation record\n %s
0x0f66 CAP definition file, wrong sequence record\n %s
0x0f67 CAP definition file, wrong pattern record\n %s
0x0f68 CAP definition file, signal cannot be binded with the dictionary\n 
0x0f69 CAP definition file, address and/or data bus signals are not definied\n 
0x0f6a CAP definition file incoherent with the dictionary\n
0x0f6b CAP definition file, several signals are dedicated for the pulse or pulse type are mixed\n
0x0f6c CAP definition file, pulse signal is not available with the current DLL socket version\n
0x0f6d Impossible to read the existing protocol, because the cluster signals have changed.
0x0f6e CAP definition file, signal could not be found. Component is probably in wrong state because of initializations script\n
0x0f6f CAP definition file %s could not be opend for reading.\n
0x0f70 Flash programming settings file cannot be opened\n
0x0f71 Flash programming envrionment already initialized\n
0x0f72 Flash programming envrionment not initialized\n
0x0f73 Input data file for flash programming cannot be opened\n
0x0f74 Input data type for flash programming unknown\n
0x0f75 Errors found during the flash programming process\n
0x0f76 Output data file for flash dumping cannot be opened\n
0x0f77 Flash erasing failed, or not finished yet, or error in read protocol\n
0x0f78 Format of input file is invalid\n
0x0f79 Missing or bad path for program file\n
0x0f7a incorrect format in the input data file for flash programming\n
0x0f7b invalid checksum in the input data file for flash programming\n
0x0f7c error while executing the init file\n
0x0f7d unknown data bus width, could not verify result of erasure\n
0x0f7e current operation aborted by user\n
0x0f7f could not initialize the UUT\n
0x0f80 %s file %s import correctly processed (test file adapted to board configuration)\n
0x0f81 %s file %s import correctly processed (test file copied without change)\n
0x0f82 Error while reading flash input data file\n
0x0f83 Flash erasure could not be initiated (component and/or access protocol should be checked)\n
0x0f84 %s file %s could not be imported\n
0x0f85 %s file %s could not be adapted during import (only tts file can modified during import).\n Board should be selected when importing such file.\n
0x0f86 Obsolete flash protocol\n
0x0f87 At flash address 0x%s: data 0x%x was written, but value 0x%x was read
0x0f88 Flash Manufacturer IDCODE could not be read (component and/or access protocol should be checked)\n
0x0f89 Flash Device IDCODE could not be read (component and/or access protocol should be checked)\n
0x0f8a Flash Manufacturer IDCODE is not defined (protocol should be checked)\n
0x0f8b Flash Device IDCODE is not defined (protocol should be checked)\n
0x0f8c Flash Reset could not be performed (component and/or access protocol should be checked)\n
0x0f8d Flash Erase is Forbidden
0x0f8e At flash address 0x%s: data 0x%x%.8x was written, but value 0x%x%.8x was read
0x0f8f Flash is still busy. Play reset.\n
0x0f90 Error while programming PLD.\n
0x0f91 Error while analysing input file for programming PLD
0x0f92 For selected flash test following protocols are needed: Reset, Read, ID Codes\n
0x0f93 For selected flash test all the protcols have to be defined.\n
0x0f94 Flash ready during erase process!\n
0x0f95 Sector erase space out of range of memory.\n
0x0f96 Sector address not valid! Access protocol should be checked.\n
0x0f97 Sector size not valid! Access protocol should be checked.\n
0x0f98 Could not communicate with I2C slave device.\n
0x0f99 Serial device is not ready.\n 
0x0f9a At address 0x%s: data 0x%x was written, but value 0x%x was read
0x1000 no valid inputs specified in signal definition file : parsing stopped!\n
0x1001 signal %s not found in the scan chain\n
0x1002 no inputs specified in the TSSI vector file : parsing stopped!\n
0x1003 wrong format line %d: parsing stopped!\n
0x1004 parse error in %s import, see log file!\n
0x1005 invalid %s for signal %s\n
0x1007 wrong vector format: parsing stopped!\n
0x1008 only digital signals can be processed: parsing stopped!\n
0x1009 wrong vector format, position %d : parsing stopped!\n
0x100a %d signal(s) have been found in the scan chain\n
0x100b TSSI vector file correctly processed for all %d lines\n
0x100c %d warning(s) found\n
0x100d %s %s file correctly analyzed\n
0x100e %d line(s) processed\n
0x1101 expression to analyze is empty\n
0x1102 number of parenthesis in expression does not match\n
0x1103 parenthesis in expression badly placed\n
0x1104 strings in expression could not be decoded\n
0x1105 operator in expression could not be decoded\n
0x1106 unknown error in expression\n
0x1107 inconsistency in expression\n
0x1108 impossible to build the expression tree: bad parenthesis match\n
0x1109 impossible to build the expression tree: operator as final node\n
0x110A impossible to evaluate the expression: tree badly constructed\n
0x110B impossible to evaluate the expression: division by 0\n
0x1110 variable '%s' will not be displayed, because its expression '%s' can not be understood\n
0x1111 Control cell %s could not be accessed. Component is probably in wrong mode (not in EXTEST). Please check console for more information. \n
0x1300 IDCODE REGISTER: idcode pattern length (%d bits) must be 32 bits
0x1400 , line %d
0x1401 LOAD: the current BSDL file '%s' is alerady loaded
0x1402 LOAD: unable to open the BSDL file '%s'
0x1403 PHYSICAL PIN MAP: DiaTem process requires a physical pin mapping. Specify it in the 'Generic' statement
0x1404 TAP SIGNAL: TCK signal has not been set
0x1405 TAP SIGNAL: TDI signal has not been set
0x1406 TAP SIGNAL: TMS signal has not been set
0x1407 TAP SIGNAL: TDO signal has not been set
0x1408 REGISTER ACCESS: opcode '%s' is not associated to a register
0x1409 PHYSICAL PIN MAP '%s': logical port '%s' is not referenced in the pin mapping
0x140a INSTRUCTION OPCODE: BYPASS, EXTEST and/or SAMPLE opcode are mandatory
0x140b IDCODE REGISTER: idcode register is defined without idcode opcode
0x140c IDCODE REGISTER: idcode pattern length (%d bits) should be modulus 32 bits (see IEEE Standard 1149)
0x140d IDCODE REGISTER: idcodes have to have the least significant bit set to 1
0x140e USERCODE REGISTER: usercode register cannot be defined if idcode register is not defined
0x140f USERCODE REGISTER: usercode register is defined without usercode opcode
0x1410 USERCODE REGISTER: usercode pattern length have to be modulus 32 bits
0x1411 BOUNDARY SCAN: cell '%d' is not defined
0x1412 BOUNDARY SCAN: control cell '%d' used in cell '%d' has not a right function
0x1413 BOUNDARY SCAN: disable values of cells '%d' and '%d' are differents
0x1414 BOUNDARY SCAN: cells '%d' and '%d' use the same logical port with the same function type
0x1415 invalid component name '%s'
0x1416 logical port '%s' already exists
0x1417 physical pin '%s' already exists
0x1418 unknown logical port '%s'
0x1419 logical port '%s' is already used in this statement
0x141a logical port '%s' doesn't match with the physical pin list
0x141b logical port '%s' has not the right dimension
0x141d logical ports are identical
0x141e logical ports have to have the same type
0x141f TAP_SCAN signal is already set
0x1420 TCK signal is already set
0x1421 pattern length doesn't match with declared port list
0x1422 instruction length must be greated or equal than %d
0x1423 DISABLE opcode '%s' not defined
0x1424 CLAMP opcode '%s' not defined
0x1425 PRIVATE opcode '%s' have to be a user instruction
0x1426 PRIVATE opcode '%s' not defined
0x1427 opcode '%s' is already affected
0x1428 pattern length doesn't match with declared instruction length
0x1429 opcode pattern value '%s' is already exists
0x142a opcode pattern value '%s' is reserved for BYPASS opcode
0x142b opcode pattern value '%s' is reserved for EXTEST opcode
0x142c bad capture pattern format: '%s'
0x142d capture pattern length doesn't match with declared instruction length
0x142e capture pattern have to have the 2 least significant bits set to '01'
0x142f register length is incompatible with the default/previous specification
0x1430 at creation time, the register length must be specified
0x1431 opcode '%s' has not been declared
0x1432 incompatible opcode '%s' and register '%s'
0x1433 ignoring opcode '%s' for register '%s'
0x1434 opcode '%s' is already associated to a register
0x1439 register '%s' and opcode '%s' association can not have a capture pattern
0x143a incompatible capture pattern and register length
0x143b boundary scan length must be greater than 0
0x143c boundary scan length already sets
0x143d '*' port name and function are incompatible
0x143e cell number '%d' out of range
0x143f multiply declarations for cell '%d'
0x1440 merged cells '%d' correspond to the same logical port
0x1441 merged cell functions are incompatible
0x1442 merged cells have to have the same cell name
0x1443 merged cells have to have the same safe bit value
0x1444 linkage logical port cannot be linked to a boundary scan cell
0x1445 logical port type and boundary cell function are incompatible
0x1446 control cell number '%d' out of range
0x1447 disable specifications are incompatible with the cell function
0x1448 function OUTPUT2 mandates that the cell number is equal to the cell control number
0x1449 disable specifications must be specified for the cell function
0x144a invalid runbist statement: runbist opcode not defined
0x144b invalid runbist wait duration
0x144c invalid runbist clock cycle
0x144d invalid intest statement: intest opcode not defined
0x144e invalid intest wait duration
0x144f invalid intest clock cycle
0x1450 unexpected 'unknown' attibute statement
0x1451 unexpected '%s' attribute statement
0x1452 unknown logical port '%s'
0x1453 logical port '%s' has an incompatible type
0x1454 logical port '%s' already used in this statement
0x1455 logical port '%s' already used in other statements
0x1456 logical port '%s' must be declared OUT
0x1457 logical port '%s' must be declared IN
0x1458 BOUNDARY SCAN: the IN logical port '%s' is never used as the boundary cell
0x1459 BOUNDARY SCAN: the OUT logical port '%s' is never used as the boundary cell
0x145a BOUNDARY SCAN: the BUFFER logical port '%s' is never used as the boundary cell
0x145b BOUNDARY SCAN: the INOUT logical port '%s' is never used as the BIDIR boundary cell
0x145c BOUNDARY SCAN: the INOUT logical port '%s' is never used as the OUTPUT boundary cell
0x145d BOUNDARY SCAN: the INOUT logical port '%s' is never used as the INPUT boundary cell
0x145e BOUNDARY SCAN: the LINKAGE logical port '%s' has not be used as the boundary cell
0x145f REGISTER ACCESS: private opcode '%s' is not associated to a register
0x1460 PHYSICAL PIN MAP '%s': linkage logical port '%s' should be referenced in the pin mapping
0x1461 BOUNDARY SCAN: control cell '%d' is not used in any disable specification
0x1462 instruction length should be less or equal than %d
0x1463 user boundary scan cell '%s' detected
0x1464 wrong VHDL identifier '%s'
0x1465 invalid VDHL name for the default device package: '%s'
0x1466 wrong range: %d TO %d
0x1467 wrong range: %d DOWNTO %d
0x1468 invalid BSDL component conformance '%s'
0x1469 pin map string parsing: initialization failed
0x146a pin map string parsing: termination failed
0x146b port group string parsing: initialization failed
0x146c port group string parsing: termination failed
0x146d compliance pattern string parsing: initialization failed
0x146e compliance pattern string parsing: termination failed
0x146f operation code table string parsing: initialization failed
0x1470 operation code table string parsing: termination failed
0x1471 private name string parsing: initialization failed
0x1472 private name string parsing: termination failed
0x1473 IDCODE name string parsing: initialization failed
0x1474 IDCODE name string parsing: termination failed
0x1475 USERCODE name string parsing: initialization failed
0x1476 USERCODE name string parsing: termination failed
0x1477 register string parsing: initialization failed
0x1478 register string parsing: termination failed
0x1479 cell table string parsing: initialization failed
0x147a cell table string parsing: termination failed
0x147b runbist specification string parsing: initialization failed
0x147c runbist specification string parsing: termination failed
0x147d intest execution sequence parsing: initialization failed
0x147e intest execution sequence parsing: termination failed
0x147f invalid disable value, should be '0' or '1'
0x1480 invalid safe bit value, should be '0', '1', or 'X'
0x1481 The pin name %s is not compliant with norm. It has to contain alphanumerical and numerical characters.\n
0x1482 The pin name %s is not alphanumerical.\n
0x1483 IR Instruction unknown, probably user instruction.\n
0x1484 use of instruction code %s for other instructions that result in entry to test mode has been deprecated
0x1485 same opcode pattern value is only tolerated for sample and preload instruction in IEEE1149.1-2001 version
0x1486 BOUNDARY SCAN: cell (%d) controlling itself need to a same level for disable result than disable value (cf. B.8.14.2-k et l)
0x1487 BOUNDARY SCAN: the safe bit value of CONTROL or CONTROLR cell %d shall be equal to disable value of cell %d (cf. B.8.14.2 - n)
0x1488 invalid BSDL AIO component conformance '%s'
0x1489 invalid extest_pulse statement: extest_pulse opcode not defined
0x148a invalid extest_pulse wait duration
0x148b invalid extest_pulse clock cycle
0x148c invalid extest_train statement: extest_train opcode not defined
0x148d invalid extest_train train number
0x148e invalid extest_train maximum time
0x14a0 extest_pulse execution sequence parsing: initialization failed
0x14a1 extest_pulse sequence parsing: termination failed
0x14a2 extest_train execution sequence parsing: initialization failed
0x14a3 extest_train sequence parsing: termination failed
0x14a4 aio pin behavior specification string parsing: initialization failed
0x14a5 aio pin behavior specification string parsing: termination failed
0x14a6 the value of port ID shall be the same value that appears in the scan port identification : %s 
0x1500 can not find entity %s in vhdl file named %s\n
0x1501 no entity found in vhdl file named %s\n
0x1502 file %s already open\n
0x1504 File %s open
0x1505 %d warning(s)\n
0x1506 Successfully read
0x1507 %d error(s)\n
0x1508 entity %s imported from file %s already exists in workspace\n
0x1509 entity %s contains no port definition in file %s\n
0x150A unable to format entity %s\n
0x150B unable to instanciate %s of component %s\n
0x150C entity %s contains instances which do not exist in the current library\n
0x150D unable to insert instruction %s in BYPASS register of entity %s\n
0x150E unable to insert instruction %s in DEVICE_ID register of entity %s\n
0x150F unable to insert instruction %s in USERCODE register of entity %s\n
0x1510 unable to insert instruction %s in boundary scan register of entity %s\n
0x1511 unable to insert instruction %s in entity %s\n
0x1512 unable to insert %s register in entity %s\n
0x1513 unknown boundary scan cell\n
0x1514 %s usercode register unsupported\n
0x1515 NetList merger correctly process\n
0x1516 Map from file correctly process\n
0x1517 Unable to instanciate the component with any port mapped. Process cancel\n
0x1518 Unable to load resource of component %s to verify instance name\n
0x1519 Instance name and port name of component %s are identical\n
0x1520 Instance name and intern signal name of component %s are identical\n
0x1521 Error in merging processus\nPlease refer to %s file in component version directory for more information\n
0x1522 Unmap correctly process\n
0x1523 Incoherency between component signal name and \nsignal name '%s' described in TruthTable file %s. Process aborted.\n
0x1524 the board or system hasn't all their components JTAG compliant (no BSDL was previously imported) or a cluster hasn't its interface completly defined. Process aborted\n
0x1525 the instance name is empty\n
0x1526 Unable to find %s.sdf file. Simulation will be made without delay consideration\n
0x1527 Unable to connect to the modelsim XE socket (Host IP adress : %s, Host port : %d)\nModelsim XE may be not started correctly\n
0x1528 Unable to create a socket to dialog with modelsim XE\n
0x1529 Parse error in file %s\nCan not list module name\n
0x1530 Parse error in file %s\nCan not list entity name\n
0x1531 Automatic map correctly process\n
0x1532 Automatic map have not be done\nNo same pins name are found\n
0x1533 Verilog library directory is not defined in settings of Mentor Graphics MSIM XE socket\nProcess stop\n
0x1534 The signal name should not be empty\n
0x1535 The signal name can only contain [A-Za-z0-9_] characters, and must not start with a '_' char or number.\n
0x1536 Please enter at least one pin name.\n
0x1537 '%s' pin name not found.\n
0x1538 '%s' : please include the chip name, as in 'U12/1'.\n
0x1539 Pin name '%s' entered more than once.\n
0x1540 The pins '%s' and '%s' have cells of different types.\n
0x1541 Could not find cell (pin %s, offset %d).\n
0x1542 Could not find net (pin %s).\n
0x1543 The nets %s and %s have different directions.\n
0x1544 Group name %s is already in use.\n
0x1545 Elements found : %d. Operation canceled.\n
0x1546 'Group by name' can't group cells of different types.\n
0x1547 BSDL export correctly processed\n
0x1548 Can not open resource file\n
0x1549 unable to load dictionary\n
0x1550 no pin label is defined for signal %s\n
0x1551 cell can not control another cell if its function is equal to %s\n
0x1552 control label name does not exist in dictionary\n
0x1553 can not find cell index in dictionary\n
0x1554 Unable to load resource port section\n
0x1555 Export %s file in %s directory correctly processed\n
0x1556 Export %s HDL file(s) to System Builder correctly process\n
0x1557 %s component is not exported in System Builder because it already exists in\n
0x1558 Tests have been modified. Save before quit ?
0x1559 JAM command succeeded \n See report in %s for more details
0x155a JAM command failed \n See report in %s for more details
0x155b SVF export file could not be created. Export cancelled.
0x155c Error while closing SVF output file.
0x155d Export SVF : Start recording. File %s opened.
0x155e Export SVF : Stop recording. File %s closed.
0x155f "Test Cluster not recording into SVF file"
0x1560 STAPL command succeeded \n See report in %s for more details
0x1561 STAPL command failed \n%s\nSee report in %s for more details
0x1562 See report in %s for help
0x1563 TSVF export file could not be created. Export cancelled.
0x1564 Error while closing TSVF output file.
0x1565 Export TSVF : Start recording. File %s opened.
0x1566 Export TSVF : Stop recording. File %s closed.
0x1600 The model for family %s and version %s is not defined!\n
0x1601 The model for instance %s is not defined!\n
0x1609 "Test aborted : socket Fatal Error"
0x1610 "Test aborted : Difference(s) found between Actual and Expected values"
0x1611 "Test aborted : pattern Match"
0x1613 "Test aborted : socket not loaded"
0x1618 "Test aborted : Unable to set TBC delay"
0x1619 "Test aborted : Unable to set signal dictionary"
0x1620 Verification failed\n
0x1621 Scan check failed
0x1622 Programming error
0x1623 Repeating vector because of result Difference(s)
0x1700 internal error, could not find value to remove net\n
0x1701 could not find signal '%s'\n
0x1800 JTAG Integrity
0x1801 Check UUT Connection ...
0x1802 UUT Connection Checking error(s)\n
0x1803 UUT Connection Successfully Checked\n
0x1901 BitPag Test Report - Starting %s\n
0x1902 Unit Under Test : %s - %s\n\n
0x1903 Netlist load : %s\n
0x1904 Netlist reduction : %s\n
0x1905 Netlist link : %s\n
0x1906 Netlist save : %s\n
0x1907 %s : file %s, line %d\n
0x1908 IEEE 1149.1 test : %s\n
0x1909 Test Vector Generation : %s\n
0x1910 Test Vector Execution : %s\n
0x1911 Net at receiver Pin %s/%s (%s[%d]) driven by Pin %s/%s (%s[%d]) is Open/stuck at %d\n
0x1912 Net at receiver Pin %s/%s (%s[%d]) driven by Pin %s/%s (%s[%d]) is in error\n
0x1913 Net at receiver Pin %s/%s (%s[%d]) driven by Pin %s/%s (%s[%d]) is shorted with :\n
0x1914      Net at driver Pin %s/%s (%s[%d])\n
0x1915      Net not identifiable (driver(s) isolated)\n
0x1917 \n
0x1918 Net at receiver Pin %s/%s (%s[%d]) is not connected to GND\n
0x1919 Net at receiver Pin %s/%s (%s[%d]) is not connected to VCC\n
0x1920 Cluster(s) Test Execution : %s\n
0x1921 Cluster %s : Ram Address Path larger then Data Path, testing only Addresses [%d:%d]\n
0x1922 Cluster %s : missing test file %s, test skipped\n
0x1923 Cluster %s : unable to open test file %s, test skipped\n
0x1924 Net at receiver Pin %s/%s (%s[%d]) driven by Cluster port %s[%d] is in error: %d instead of %d\n
0x1925 %s Test(s) on Cluster %s\n
0x1926 Not yet implemented, test skipped\n
0x1927 Functional test(s) Execution : %s\n
0x1928 Net at receiver Pin %s/%s (%s[%d]) is in error: %d instead of %d\n
0x1929 The cluster '%s' has not been tested because it has not been defined\n
0x192A Standard Cluster Library directory not defined in Preferences\n
0x192C Failed to export cluster model\n
0x192D BSDL Library directory not defined in Preferences\n
0x192E Path directory of tested BSDL files must be different from BSDL Library path directory defined in Preferences\n
0x192F BSDL Test ended with no erros\n
0x1930 Processing Stopped\n
0x1931 Number Of Open(s)/Stuck(s) : %d\n
0x1932 Number Of Short(s)         : %d\n
0x1933 Number Of GND Fault(s)     : %d\n
0x1934 Number Of VCC Fault(s)     : %d\n
0x1935 Number Of Other Fault(s)   : %d\n\n
0x1936 TOTAL NUMBER OF ERROR(S) = %d\n
0x1937 BitPag Test Report - Ending %s\n
0x1938 Skipping test of pure JTAG components\n
0x1939 Net at receiver Pin %s/%s (%s[%d]) driven by Pin %s/%s (%s[%d]) cannot be tested for short. Driver pin is not bidirectional\n
0x193B Library not installed on disc\n
0x193C Cluster already imported in the library\n
0x1940 Error on control net(s). Cannot test Data path for open(s)\n
0x1941 The cluster '%s' has not been tested because an error happened during execution of its init file\n
0x1942 PASSED
0x1943 FAILED
0x1944 Scan Integrity Test Report - %s\n
0x1945 Unit Under Test : %s - %s\n
0x1946 TCK Speed : %d ns\n
0x1947 Set the TBC Delay:\n
0x1948  Unable to set TBC delay, forced to %d bit\n
0x1949   %d delay bit(s) found\n
0x194A Set TBC Delay %s\n
0x194B Check global IR size:\n
0x194C   Unable to calculate the size, expected %d bits\n
0x194D   Wrong size, %d bit(s) found instead of %d bits\n
0x194E   %d bits found\n
0x194F Check global IR size %s\n
0x1950 Check the components number:\n
0x1951   Unable to find the number of components, expected %d\n
0x1952   Wrong number of component, %d found instead of %d\n
0x1953   %d component(s) found\n
0x1954 Check components number %s\n
0x1955 Check the two IR LSB (the standard defines '01'):\n
0x1956   Instance %s of %s %s, read '%c%c' %s\n
0x1957 Check IR LSB %s\n
0x1958 Check the IR signature:\n
0x1959   Instance %s of %s %s, read 0x%X, expected 'undefined'\n
0x195A   Instance %s of %s %s, read 0x%X, expected 0x%X, mask 0x%X %s\n
0x195B Check IR signature %s\n
0x195C   --- try to check IR signatures in revers order ---\n\n
0x195D   *** probably there is a open or stuck at '%c' here ***\n
0x195E   *** probably the next component is not IEEE1149 compliant ***\n
0x195F   *** probably due to the wrong definition in the component database (BSDL, ...) ***\n
0x1960 Check the Device ID:\n
0x1961   Instance %s of %s %s, Device ID not implemented\n
0x1962   Instance %s of %s %s, expected value undefined\n
0x1963   Instance %s of %s %s, unable to calculate the size, expected %d bit(s)\n
0x1964   Instance %s of %s %s, wrong size, %d bit(s) found instead of %d bit(s)\n
0x1965   Instance %s of %s %s, read %s, expected %s, mask %s %s\n
0x1966 Check Device ID %s\n
0x1967 Check the Boundary Scans:\n
0x1968   Instance %s of %s %s, Sample/Preload instruction not implemented\n
0x1969   Instance %s of %s %s, unable to calculate the size, expected %d bit(s)\n
0x196A   Instance %s of %s %s, wrong size, %d bit(s) found instead of %d bit(s)\n
0x196B   Instance %s of %s %s, %d bit(s) found\n
0x196C Check Boundary Scans %s\n
0x196D Check the registers of the instance %s of %s %s:\n
0x196E   %s by using instruction %s, unable to calculate the size, expected %d bit(s)\n
0x196F   %s by using instruction %s, wrong size, %d bit(s) found instead of %d bit(s)\n
0x1970   %s by using instruction %s, %d bit(s) found\n
0x1971 Check registers %s\n
0x1972 SCAN CHAIN INTEGRITY STATUS: %s\n
0x1973 Scan Integrity Test completed at %s\n
0x1974 ERROR
0x1975 WARNING
0x1976 PASSED
0x1977 FAILED
0x1978 Problem in the JTAG chain.\nCheck power, cables, or see report.
0x1979 Could not execute JTAG integrity check. See report.
0x197A JTAG Interconnect
0x197B Cluster Interconnect
0x197C Group
0x197D Frequency
0x197E Test
0x197F Minimum operating frequency
0x1980 Nominal frequency
0x1981 Minimum frequency
0x1982 Step
0x1983 Result
0x1984 Operator guidance
0x1985 Not found
0x1986 Component
0x1987 Signal
0x1988 Expected
0x1989 Mask
0x198A Actual
0x198B Pin
0x198C Process
0x198D FAILED
0x198E COULD NOT RUN
0x198F ok
0x1990 canceled by user
0x1991 not executed
0x1992 Pin %s/%s is shorted with Net not identifiable%s\n
0x1993 Pin %s/%s is shorted with pin %s/%s\n
0x1994 Netlist error: component instance %s not found for pin %s when linking\n
0x1995   (Related nets: %s)\n
0x1996 ### Warning : Net deleted because the pin name '%s' appearing in the netlist is not connected to a jtag pin (component %s (%s, NLRef %s), NL pin name %s)\n
0x1997   *** following result is incoherent with the previous error. Please check your JTAG connection: cable, frequency, noise... ***\n
0x1999 %d net(s) have been removed by the vector generation. See file '%s' for details.
0x1A01 JTAG & Cluster Interconnect
0x1A02 Loading Netlist ...
0x1A03 Netlist Successfully Loaded\n
0x1A04 Netlist Loading error(s), see report\n
0x1A05 Reducing Netlist ...
0x1A06 Netlist Successfully Reduced\n
0x1A07 Netlist Reducing error(s), see report\n
0x1A08 Linking NetList ...
0x1A09 NetList Successfully Linked\n
0x1A10 Netlist Linked error(s)\n
0x1A11 NetList Saving  ...
0x1A12 NetList Sucessfully saved\n
0x1A13 NetList Saving error(s), see report\n
0x1A14 Checking IEEE 1149.1 Integrity ...
0x1A15 IEEE 1149.1 Integrity Successfully Checked\n
0x1A16 IEEE 1149.1 Integrity Checking error(s), see report\n
0x1A17 Generating Test Vectors ...
0x1A18 Test Vectors Successfully Generated\n
0x1A19 ### Missing .rnl file, or no net in .rnl file ###\n
0x1A20 Running Test Vectors...
0x1A21 Test Vectors Successfully Run\n
0x1A22 Test Vectors Running error(s), see report\n
0x1A23 Running Cluster(s) Test...
0x1A24 Cluster(s) Test Successfully Run\n
0x1A25 Cluster(s) Test Running error(s), see report\n
0x1A28 Test specific testable nets...\n
0x1A29 Test specific testable nets ended\n
0x1A2A TUC "%s"\n
0x1A30 Processing Started %s\n
0x1A31 %%H:%%M:%%S
0x1A32 Processing Completed %s\nProcessing time : %s
0x1A33 %#c
0x1A34 [%s] %s
0x1A35         -->  %s
0x1A38 Warnings found (see file BitPag.txt).\r\n
0x1A39 <LI> Cluster signal %s[%d] (controlled by Pin %s) is opened%s<BR>\n
0x1A3A Cluster %s : Can't test opens because could not perform R/W. Possible causes : missing component on board, missing initialisation script, error in signal declaration, one or more of the control nets is opened (or shorted if not tested before), error in read/write/refresh protocol, max clock period exceeded. Please check initialsation script\n
0x1A3B Opened%s
0x1A3C unable to test opens for %s cluster %s, because the clock is free-running\n
0x1A3D  or shorted (with an undetermined net)
0x1A3E Shorted with : 
0x1A3F Net not identifiable
0x1A40 Pin in error
0x1A41 Pin in error (%d instead of %d)
0x1A42 Not connected to VCC
0x1A43 Not connected to GND
0x1A44 , or stuck at 0.
0x1A45 , or stuck at 1.
0x1A46 Netlist of cluster %s could not be initialized properly. Please check component(s) initialization state. 
0x1A47 Error while evaluating rules (%s).\n
0x1A48 Library not found for instance "%s". Please re-create instance.  
0x1B00 Unable to start the waveform generator process for %s,\na process is currenlty running for %s\n
0x1B01 Unable to perform this command for %s,\nits waveform generator process is not running\n
0x1B02 System error during the waveform generator process creation for %s: \n%s\n
0x1B03 The waveform index is out of range for %s: max %d\n
0x1B04 System error during external viewer launching\n
0x1B05 External viewer launching error\n
0x1B06 The viewer path is incorrect : %s doesn't exist\n
0x1B07 Waves are displayed only if at least 1 signal is selected
0x1B10 External net viewer launching error. Check InterComm setup and license.
0x1BD1 <BR>==><U>Test aborted</U>
0x1BD2 <BR>==><U>Test aborted due to error while running test script</U>
0x1C00 Processing start: <EM>%s</EM><BR>\n
0x1C01 Connectivity test report
0x1C02 Unit Under Test: <STRONG>%s</STRONG><BR>\n\n
0x1C03 <LI>Netlist load : %s\n<UL>
0x1C04 <LI>Netlist reduction : %s<BR>\n
0x1C05 </UL>\n<LI>Netlist link : %s\n<UL>
0x1C06 Netlist save : %s\n
0x1C07 %s : file %s, line %d\n
0x1C08 </UL>\n<LI>IEEE 1149.1 test : %s\n<UL>
0x1C09 </UL>\n<LI>Test Vector Generation : %s\n<UL>
0x1C0A <LI>With TUC "%s"\n<OL type=i><BR>\n
0x1C0B </UL>\n<LI>Check UUT Connection : %s\n<UL>
0x1C10 </UL>\n<LI>Test Vector Execution : %s\n<UL>
0x1C11 <LI>Net at receiver Pin %s (%s) driven by Pin %s (%s) is Open/stuck at %d<BR>\n
0x1C12 <LI>Net at receiver Pin %s (%s[%d]) driven by Pin %s (%s[%d]) is in error<BR>\n
0x1C13 <LI> Net at receiver Pin %s (%s) driven by Pin %s (%s) %sis shorted with <BR>\n
0x1C14  Net at driver Pin %s (%s)\n
0x1C15  Net not identifiable (driver(s) isolated)\n
0x1C18 <LI> Net at receiver Pin %s (%s) is not connected to GND<BR>\n
0x1C19 <LI> Net at receiver Pin %s (%s) is not connected to VCC<BR>\n
0x1C20 </UL>\n<LI> Cluster(s) Test Execution : %s <BR>\n
0x1C21 <LI> Cluster %s : Ram Address Path larger then Data Path, testing only Addresses [%d:%d]<BR>\n
0x1C22 <LI> Cluster %s : missing test file %s, test skipped<BR>\n
0x1C23 <LI> Cluster %s : unable to open test file %s, test skipped<BR>\n
0x1C24 <LI> Net at receiver Pin %s (%s) driven by Cluster port %s[%d] is in error: %d instead of %d<BR>\n
0x1C25 &nbsp; &nbsp; <i><b>%s Test(s) on Cluster %s:</b></i>\n<UL>
0x1C26 <LI> Not yet implemented, test skipped<BR>\n
0x1C27 <LI> Functional test(s) Execution : %s<BR>\n
0x1C28 <LI> Net at receiver Pin %s/%s (%s[%d]) is in error: %d instead of %d<BR>\n
0x1C29 <LI> The cluster '%s' has not been tested because it has not been defined<BR>\n
0x1C31 <TR><TH>Number Of Open(s)/Stuck(s) : <TH>%s%d</STRONG>\n
0x1C32 <TR><TH>Number Of Short(s) : <TH>%s%d</STRONG>\n
0x1C33 <TR><TH>Number of GND Fault(s) : <TH>%s%d</STRONG>\n
0x1C34 <TR><TH>Number Of VCC Fault(s) : <TH>%s%d</STRONG>\n
0x1C35 <TR><TH>Number of Other Fault(s) : <TH>%s%d</STRONG>\n
0x1C36 <TR><TH><STRONG>TOTAL NUMBER OF ERROR(S) : </STRONG><TH>%s%d</STRONG>\n
0x1C42 <STRONG style="color: green">PASSED</STRONG>
0x1C43 <STRONG style="color: red">FAILED</STRONG>
0x1C78 Warnings found (see file BitPag.txt).\r\n
0x1C92 <LI> Cluster signal %s/%s (controlled by Pin %s) is shorted with Net not identifiable%s<BR>\n
0x1C93 <LI> Cluster signal %s/%s (controlled by Pin %s) is shorted with Cluster signal %s/%s (controlled by Pin %s)<BR>\n
0x1C94 Netlist error: component instance %s not found for pin %s when linking\n
0x1C95 [Related net(s): %s] 
0x1C96 ### Warning : Net deleted because the pin name '%s' appearing in the netlist is not connected to a jtag pin (component %s (%s, NLRef %s), NL pin name %s)<BR>\n
0x1C97 No error found.
0x1C98 </UL>\n<LI>Additional testable nets:\n<OL type=I>
0x1C99 <B><I>WARNING:</I></B> %d net(s) have been removed by the vector generation. See file '%s' for details.
0x1CFF Processing end: <EM>%s</EM><BR>\n
0x2000 Automatic map between connector %s and connector %s
0x2001 Mapping with map file between board %s and board %s
0x2002 Manual map between connector %s and connector %s
0x2003 Reset all pins connector association between connector %s and connector %s
0x2004 Reset all pins connector association
0x2005 Can not find dnl file for board or system %s
0x2006 As the system have a netlist, it must be at least selected
0x2007 You already choose two boards to merge, so you can not choose other board before executing merge process
0x2008 Can not proceed to automatic map between connector %s and connector %s
0x2009 Can not proceed to merge due errors
0x200a Can not save merged netlist
0x200b You can not choose connectors which belong to the same board
0x200c Can not proceed to manual map between connector %s and connector %s
0x200d Unable to load the project database. Process stops
0x200e Unable to load the socket database. Process stops
0x200f Unable to plug IP component in socket. Process stops
0x2010 Checking IP failed. Process stops
0x2011 Unable to get the IP identification code or it is differed from the waited code. Process stops
0x2012 Checking IP process is done\nPress OK to continue
0x2013 No need to init IP, press OK to continue
0x2014 can not add ip because you already reach the max number of ip that can be inserted\n
0x2015 the selected %s entity is considered as user top level due to multiple top level declared in design browser tree\n
0x2016 Load %s file\n
0x2017 There is multiple top level declared in design browser tree.\nPlease select the top level you want to instrument in this tree and rerun process.\nProcess stop\n
0x2018 can not affect N signals with M IP signals\n
0x2019 can not affect signals because the number of selected signals from design is upper than IP signals I can affect\n
0x201A Unable to evaluate the signal width of %s\n
0x201B Debug can not be performed if project is not saved. \nPlease, save first the project %s \n(If instrumentation changed, also synthesize it prior debugging the target)\n
0x201C Stopping infinite recursion detected between entities %s and %s (see %s)\n
0x201D Stopping infinite recursion in entity %s (see file %s)\n
0x201E Cannot use a package as a top level design, please select another entity from the design tree\n
0x201F Cannot connect a signal mapped to OPEN (%s)\n
0x2020 Debug can not be performed using an obsolete instrumentation\nPrior debugging the target, please:\n - Finish or fix the instrumentation for project %s\n - Save the project\n - Synthesize it\n
0x2021 Please select the top level source from the active project prior generating
0x2022 Could not create association between %s and %s\nPlease check for conflicts with existing associations\n
0x2023 The following project has no default library:\n%s\n
0x2024 The project\n%s\nfeatures an invalid library:\n%s\n
0x2025 There is no top level design.\n
0x2026 Could not load Netlist. %s
0x2027 File %s does not exist yet. Do you want to create it or import another one ?
0x2028 File %s could not be created. Please check directory write access.
0x2029 File %s already exist but not attached to instance. Do you want to edit it or import another one?
0x202a File %s has been copied and renamed into IN directory : %s!
0x202b File %s could not be copied into IN directory :\n%s!
0x2100 Could not load navigator net list: %s.
0x2101 Can not open net navigator: board net list has not been analysed yet.
0x2102 Full Net List file already exists. Do you want to update it ?
0x2103 Unable to load database %s because number of TAP exceeds licenced value.
0x2104 Uut have to be connected to use links
0x2105 Netlist analysis not found. Please do a netlist analysis before.\n
0x2106 Netlist rules file not found. Default rules will apply.
0x2107 Parse error in Netlist rules %s 
0x2108 Some information is missing. Please run again netlist analysis.
0x2109 Unable to load database %s because a licensed is not provided for a component of this database.
0x210A An error occurs for instance %s of model %s. Maybe this instance is already used. Please check the instances of the board %s.
0x210B Netlist analysis not found. tcl instructions about clusters will generate errors.\n
0x210C Netlist analysis not found. Defect Database not available.\n
0x3000 Cannot rename %s because the associated directory can not be renamed. Please close all documents from this directory and retry.\n
0x5000 [%s]: entity %s imported from file %s already exists in workspace\nProcess stop\n
0x6000 Stuck at %d
0x6001 Open between
0x6002 Open, or stuck at %d
0x6003 Short with
0x6004 Not at %s
0x6005 In error
0x6006 in file 
0x7000 Convertion from CLSID to String failed
0x7001 Can't load DiaTem type library
0x7002 Net "%s" removed from the Nets list : %s
0x8000 IP %s initialized with default value. Please enter your conditions in IP windows\n
0x8001 Error during tree load\n
0x8002 Traffic Analyser must be stopped before closing window\n
0x8003 An array has been detected in your design : \nThis %s signal can be intrumented only if it is used as a register.\nIf it represents a RAM, instrumenting one bit of it will force to synthetize it as a register rather than a RAM\n
0x8004 Signal(s) %s of type %s will not be available for connection. RAM or ROM cannot be directly instrumented\n
0x8005 Signal(s) %s of type %s will not be available for connection. This type is not supported\n
0x8006 Signal(s) %s will not be available for connection. Multi Dimensional Array is not supported\n
0x8007 Signal(s) %s will not be available for connection. Array of %s is not supported\n
0x8008 Signal(s) %s will not be available for connection. %s type is not supported\n
0x8009 Can not access to file %s in project directory\n
0x8010 Can not know if the HDL file %s is described in Verilog or VHDL language\nOnly file extensions <vhdl, vhd> for VHDL or <v> for Verilog are recognized\n
0x8011 Entity %s already exists in the %s library unit.\nEntity import cancelled.\nPlease remove first existing entity before importing file %s\n
0x8012 Error(s) during database generation process\n
0x8013 The signal %s mapped to the signal %s you want to observe is not declared as internal signal or signal interface\nWe assume it is an implicit wire signal (not a vector).\nIf it is not the case, please correct your design and add the signal declaration\n
0x8014 A signal %s you want to observe is mapped to nothing in instance %s\n
0x8015 %s is an INOUT signal. Be careful when you instrument it.\nSynthetizer may not recognize it in some cases.\nPlease refer to Reference Manual for more details\n
0x8016 You are using history or/and transaction register IPs for an Altera device.\nAs you choose to implement RAM as a primitive model and to synthetize with other EDA tools than Quartus native,\nplease create in your Quartus project the following parameterized modules (LPM) functions by using the MegaWizard\nPlug-In Manager. For more details follow the recommendations of the reference manual\n%s\n
0x9000 Could not execute command : %s\n
0x9001 Error while saving log file\n
0x9002 Check the connection to the UUT and/or the UUT power up\n
0x9003 Failed importing %d file(s) out of %d\n
0x9004 Could not generate instrumentation (some IP are not properly defined)\n
0x9005 Project or project name already exists\n
0x9006 Unexpected board definition, please check your project\n
0x9007 Project already exists - Workspace will not open\n
0x9008 Unable to observe IP/clk signal\n
0x9009 Unable to use this signal as clk: it is already used as observed signal\n
0x9010 ComCtl32 version is too old\n
0x9011 ComCtl32 is not present\n
0x9012 %s instance in %s entity has more mapped ports than those declared in its correspondent entity (file %s)\n
0x9013 Failure during load VHDL file because language licence could not be granted\n
0x9014 Failure during load Verilog file because language licence could not be granted\n
0x9015 No %s port declared in %s entity. Wrong port mapping in %s instantiation of %s (file %s)\n
0x9016 Found %s instance with more mapped ports than those declared in the correspondant entity (file %s)\n
0x9017 Incomplete %s signals connection in IP %s\nPlease finish the connection\n
0x9018 At least one clocked IP must exist to generate intrumentation\n
0x9019 Could not create file %s\n
0x9020 Could not copy file\n
0x9021 No file found for copy\n
0x9022 No Trig condition is specified for your %s history register IP\nPlease connect it to a Trig IP in Flag mode as required with history register\n
0x9023 Your %s Trig IP is connected to a history register IP and is set in Pulse mode\nPlease set this Trig IP in Flag mode as required with history register\n
0x9024 No Trig condition is specified for your %s transaction register IP\nPlease connect it to a Trig IP in Pulse mode as required with transaction register\n
0x9025 Your %s Trig IP is connected to a transaction register IP and is set in Flag mode\nPlease set this Trig IP in pulse mode as required with transaction register\n
0x9026 Could not copy file %s as it already exists (%s)\n
0x9027 Could not copy file %s to %s\n
0x9028 IP name (%s) already used\n
0x9029 Invalid name syntax (%s)\n
0x9030 Invalid empty IP name\n
0x9031 Cluster Interface Definition not complete! Following signals are NC:\n%s
0x904f Data not available (pin direction, control cell already used).
0x9050 The signal "%s" is controlled by control cell number %d already used by %s signal : "%s"
0x9051 This signal's controll cell is already used (see report console).
0x9052 The old cluster interface can not be loaded, instance %s not found\n
0x9053 Output pin %s was not connected to a cluster pin and can not be put in safe mode during cluster test. Such case may be provided unpredictable behavior
0x9054 If board or system need to be configured before cluster test, use menu 'Cluster/Initialized script' to create a tcl file
0x9055 Component with transparency table rules need to be declared as passive. It will be set in bypass mode during interconnect process. All testable nets will become in such case untestable
0x9056 To take into account check state change, please click on algo tab and "Update tested tracks" button
0x9057 no find PartValue property which contain %s in EDIF file %s
0x9058 Erreur while converting file to Edif : %i (%s)
0x9059 Cap file loading failed. Check flash access protocol
0x905a Rules import failed: %s
0x805a SPI configuration loading failed. Check SPI configuration
0x905B Some of signals enabled are not visible. Please take care of their output values
0x905C Bundle signal name %s already exist. Process stopped
0x905D No signals to bundle or signals are incompatible. Process canceled
0x905E Unable to save wave configuration file %s
0x905F Unable to load wave configuration file %s
0xA001 Test Coverage Report
0xA002 Temento Systems - %s<BR>\n
0xA003 Test coverage report generated on <EM>%s</EM><BR>\n
0xA004 <!--\nNet List file: %s\n-->\n
0xA005 <!--\nNet List rules file : %s\n-->\n
0xA006 <!--\nTuc file : %s\n-->\n
0xA007 <!--\nCluster files : %s -->\n
0xA008 <TR>\n <TH>%s</TH>\n <TD><em>%d</em></TD>\n <TD>%d</TD>\n <TD>%s</TD>\n</TR>\n
0xA009 <TR>\n <TH><A HREF="Type:%s&Testable:Yes">%s</A> </TH>\n <TD>%d</TD>\n <TD>%d</TD>\n <TD>%s</TD>\n</TR>\n
0xA00A <TR>\n <TH><A HREF="Type:%s&Testable:No">%s</A> </TH>\n <TD>%d</TD>\n <TD>0</TD>\n <TD>N/A*</TD>\n</TR>\n
0xA00B <TR>\n <TH><A HREF="Testable:Yes">%s</A> </TH>\n <TD>%d</TD>\n <TD>%d</TD>\n <TD><strong>%s</strong></TD>\n</TR>\n
0xA00C <TR>\n <TH><A HREF="Type:%s&Testable:Yes">%s</A> </TH>\n <TD>%d</TD>\n <TD>%d*</TD>\n <TD>%s</TD>\n</TR>\n
0xA010 <BR>\n<em>*JTAG Scan Chain (TDI, TDO, TMS, TCK, TRST).</em>\n<BR>\n
0xA011 <TR>\n <TH>%s</TH>\n<TD>%s</TD>\n</TR>\n
0xA012 <BR><em>**This is the maximum test coverage using JTAG (Type I, II, III, V and VI / Total number of nets).</em><BR>\n
0xA013 <BR><em>***This value shows your test achievement (Test coverage/Maximum test coverage).</em><BR>\n
0xA020 <TD>%d</TD>\n
0xA021 <A HREF="Net:%s">%s</A><BR>\n
0xA022 <TD>%s </TD>\n
0xA023 <A HREF="Component:%s&Pin:%s">%s</A><BR>\n
0xA024 <A HREF="Component:%s">%s</A><BR>\n
0xffff internal error: unknown message number %04x\n